The IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE STD 1149.1) is a well known IEEE test standard that provides scan access to scan registers within integrated circuits (ICs), and is hereby incorporated herein by reference. FIG. 12 shows a schematic of the 1149.1 test logic. The test logic comprises a TAP controller 120, an instruction register, and plural test data registers. The TAP controller is connected to test mode select (TMS), test clock (TCK), and test reset (TRST*) pins. The TAP controller responds to control input on TCK and TMS to scan data through either the instruction or data registers, via the test data input (TDI) and test data output (TDO) pins. TRST* is an optional pin used to reset or initialize the test logic, i.e. TAP controller, instruction register, and data registers. The inputs to the instruction and data registers are both directly connected to the TDI input pin. The output of the instruction and data registers are multiplexed to the TDO pin. During instruction register scans, the TAP controller causes the multiplexer 121 to output the instruction register on TDO. During data register scans, the TAP controller causes the multiplexer 121 to output the data register on TDO. The instruction scanned into the instruction register selects which one of the plural data registers will be scanned during a subsequent data register scan operation. When the TAP controller is scanning data through the instruction or data registers, it outputs control to enable the output stage to output data from the TDO pin, otherwise the TAP controller disables the output stage.
FIG. 13 shows how four ICs, each IC including the TAP controller, instruction register, and data registers of FIG. 12, would be connected at the board level for serial data transfer (TDI, TDO) and parallel control (TMS, TCK).
FIG. 14 shows the state diagram operation of the FIG. 12 TAP controller. The TAP controller is clocked by TCK and responds to TMS input to transition between its states. The logic state of TMS is shown beside the paths connecting the states of FIG. 14. The Test Logic Reset state is where the TAP controller goes to in response to a power up reset signal, a low on TRST*, or an appropriate TMS input sequence. From Test Logic Reset the TAP controller can transition to the Run Test/Idle state. From the Run Test/Idle state the TAP controller can transition to the Select DR Scan state. From the Select DR Scan state, the TAP controller can transition into a data register scan operation or to the Select IR scan state. If the transition is to the data register scan operation, the TAP controller transitions through a Capture DR state to load parallel data into a selected data register, then shifts the selected data register from TDI to TDO during the Shift DR state. The data register shift operation can be paused by transitioning to the Pause DR state via the Exit1 DR state, and resumed by returning to the Shift DR state via the Exit2 DR state. At the end of the data register shift operation, the TAP controller transitions through the Update DR state to update (output) new parallel data from the data register and thereby complete the data register scan operation. From the Update DR state, the TAP controller can transition to the Run Test/Idle state or to the Select DR Scan state.
If the Select IR Scan state is entered from the Select DR Scan state, the TAP controller can transition to the Test Logic Reset state or transition into an instruction register scan operation. If the transition is to an instruction register scan operation, Capture IR, Shift IR, optional Pause IR, and Update IR states are provided analogously to the states of the data register scan operation. Next state transitions from the Update IR state can be either the Run Test/Idle state or Select DR Scan state. If the TAP controller transitions from the Select IR Scan state into the Test Logic Reset state, the TAP controller will output a reset signal to reset or initialize the instruction and data registers.
FIG. 15 shows that state transitions of the FIG. 12 TAP controller occur on the rising edge of the TCK and that actions can occur on either the rising or falling edge of TCK while the TAP controller is in a given state.
The term TAP referred to hereafter will be understood to comprise a TAP controller, an instruction register, test data registers, and TDO multiplexing of the general type shown in FIG. 12, but differing from FIG. 12 according to novel features of the present invention described with particularity herein. The 1149.1 standard was developed with the understanding that there would be only one TAP per IC. Today, ICs may contain multiple TAPs. The reason for this is that ICs are being designed using embedded megamodule cores which contain their Own TAPs. A megamodule is a complete circuit function, such as a DSP, that has its own TAP and can be used as a subcircuit within an IC or as a standalone IC. An IC that contains multiple megamodules therefore has multiple TAPs.